06 SVE · reduction
UADDV
Active lanes fold one by one into the scalar d0; the total is their sum.
uaddv d0, p0, z0.sTypes: z0.s — 32-bit lanes, summed as unsigned integers, 4 of them; d0 — the 64-bit scalar result. The sum never overflows into a 32-bit answer, which is why uaddv is a scalable reduction. Drawn at SVL = 128 bits; at SVL = 512 the sum covers 16 lanes.
p0/m
z0.s
d0
d0 = Σ z0.s[i] over the active lanes
Ready. d0 is zero; the sum has not started.
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Reading the picture
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Vertical to horizontal
FMLA and FMOPA work along lanes; uaddv collapses the lanes into one scalar. A reduction is the vector answer to “what is the total?”. The integer form walks the lanes in order, so this one-by-one fold is the order the hardware uses; the floating-point twin faddv reduces pairwise instead.
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The predicate picks the lanes
p0 chooses which lanes join the sum — click a bit and that lane is treated as zero. There is no /m or /z here: the destination is a scalar that is always fully written, so a reduction has nothing to merge into. Inactive lanes count as zero, which is how the sum skips them.
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A family of reductions
The same shape covers saddv (signed) and faddv, fmaxv, fminv for floats — but only the integer reductions write the 64-bit d0; the float ones write an element-sized scalar, s0 for .s. The one that starts from an existing scalar instead of zero is fadda, the accumulating form.
This pass sums z0.s = {3, 1, 4, 2}.